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| 1996, 2000 data sheet 4-bit single-chip microcontroller m pd753012a, 753016a, 753017a mos integrated circuit description the m pd753017a is one of the 75xl series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. it has an on-chip lcd controller/driver with a larger rom capacity and extended cpu functions compared with the conventional m pd75316b, and can provide high-speed operation at a low supply voltage of 1.8 v. it can be supplied in a small plastic tqfp package (12 12 mm) and is suitable for small sets using lcd panels. detailed descriptions of functions are provided in the following document. be sure to read the document before designing. m pd753017 users manual : u11282e features ? low voltage operation: v dd = 1.8 to 5.5 v can be driven by two 1.5 v batteries ? on-chip memory program memory (rom): 12288 8 bits ( m pd753012a) 16384 8 bits ( m pd753016a) 24576 8 bits ( m pd753017a) data memory (ram): 1024 4 bits application remote controllers, camera-integrated vcrs, cameras, gas meters, etc. document no. u11662ej2v0ds00 (2nd edition) date published july 2000 n cp(k) printed in japan ? capable of high-speed operation and variable instruction execution time for power saving 0.95, 1.91, 3.81, 15.3 m s (at 4.19 mhz operation) 0.67, 1.33, 2.67, 10.7 m s (at 6.0 mhz operation) 122 m s (at 32.768 khz operation) ? internal programmable lcd controller/driver ? small plastic tqfp (12 12 mm) suitable for small sets such as cameras ? one-time prom: m pd75p3018a the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points. in this document, unless otherwise specified, the description is made based on m pd753017a as typical product.
2 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 ordering information part number package m pd753012agc-xxx-3b9 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd753012agc-xxx-8bt 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd753012agk-xxx-be9 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd753012agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.00 mm) m pd753016agc-xxx-3b9 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd753016agc-xxx-8bt 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd753016agk-xxx-be9 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd753016agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.00 mm) m pd753017agc-xxx-3b9 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd753017agc-xxx-8bt 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd753017agk-xxx-be9 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd753017agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.00 mm) remark xxx indicates rom code suffix. 3 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 function outline parameter function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (main system clock: at 4.19 mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (main system clock: at 6.0 mhz operation) ? 122 m s (subsystem clock: at 32.768 khz operation) internal memory rom 12288 8 bits ( m pd753012a) 16384 8 bits ( m pd753016a) 24576 8 bits ( m pd753017a) ram 1024 4 bits general purpose register ? 4-bit operation: 8 4 banks ? 8-bit operation: 4 4 banks input/ cmos input 8 on-chip pull-up resistors can be specified by using output cmos input/output 16 software: 23 port cmos output 8 also used for segment pins n-ch open-drain 8 withstands 13 v, on-chip pull-up resistors can be specified by using mask input/output option total 40 lcd controller/driver ? segment number selection : 24/28/32 segments (can be changed to cmos output port in 4 time-unit; max. 8) ? display mode selection : static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) on-chip split resistor for lcd drive can be specified by using mask option timer 5 channels ? 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter, carrier generator, timer with gate) ? basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode ... msb or lsb can be selected for transferring first bit ? 2-wire serial i/o mode ? sbi mode bit sequential buffer 16 bits clock output (pcl) ? f , 524, 262, 65.5 khz (main system clock: at 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: at 6.0 mhz operation) buzzer output (buz) ? 2, 4, 32 khz (main system clock: at 4.19 mhz operation or subsystem clock: at 32.768 khz operation) ? 2.93, 5.86, 46.9 khz (main system clock: at 6.0 mhz operation) vectored interrupt external: 3, internal: 5 test input external: 1, internal: 1 system clock oscillator ? ceramic or crystal oscillator for main system clock oscillation ? crystal oscillator for subsystem clock oscillation standby function stop/halt mode power supply voltage v dd = 1.8 to 5.5 v package ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm) 4 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 contents 1. pin configuration (top view) ................................................................................................ ..... 6 2. block diagram ............................................................................................................... ................ 8 3. pin function ................................................................................................................ .................... 9 3.1 port pins ................................................................................................................... ................... 9 3.2 non-port pins ............................................................................................................... ............. 11 3.3 pin input/output circuits ................................................................................................... ...... 13 3.4 recommended connection for unused pins ......................................................................... 15 4. switching function between mk i mode and mk ii mode ......................................... 16 4.1 differences between mk i mode and mk ii mode .................................................................... 16 4.2 setting method of stack bank select register (sbs) ........................................................... 17 5. memory configuration ........................................................................................................ ....18 6. peripheral hardware functions ....................................................................................... 23 6.1 digital input/output ports .................................................................................................. ...... 23 6.2 clock generator ............................................................................................................. ...........24 6.3 subsystem clock oscillator control functions .................................................................... 25 6.4 clock output circuit ........................................................................................................ ......... 26 6.5 basic interval timer/watchdog timer ..................................................................................... 27 6.6 watch timer ................................................................................................................. .............28 6.7 timer/event counter ......................................................................................................... ........ 29 6.8 serial interface ............................................................................................................ .............. 33 6.9 lcd controller/driver ....................................................................................................... ........ 35 6.10 bit sequential buffer ...................................................................................................... .......... 37 7. interrupt function and test function .......................................................................... 38 8. standby function ............................................................................................................ ........... 40 9. reset function .............................................................................................................. .............. 41 10. mask option ................................................................................................................ .................. 44 11. instruction set ............................................................................................................ ............... 45 12. electrical specifications .................................................................................................. .... 57 13. characteristics curves (reference values) .............................................................. 71 14. package drawings ........................................................................................................... .......... 73 15. recommended soldering conditions ................................................................................ 77 5 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 appendix a. m pd75316b, 753017a and 75p3018a function list ........................................... 79 appendix b. development tools ................................................................................................ 81 appendix c. related documents ................................................................................................ 85 6 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 note connect the ic (internally connected) pin directly to v dd . 1. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd753012agc-xxx-3b9, 753012agc-xxx-8bt, 753016agc-xxx-3b9, 753016agc-xxx-8bt m pd753017agc-xxx-3b9, 753017agc-xxx-8bt ? 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd753012agk-xxx-be9, 753012agk-xxx-9eu, 753016agk-xxx-be9, 753016agk-xxx-9eu m pd753017agk-xxx-be9, 753017agk-xxx-9eu s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 p60/kr0 x2 x1 ic note xt2 xt1 v dd p33 p32 p31/sync p30/lcdcl p23/buz p22/pcl/pto2 p21/pto1 p20/pto0 p13/ti0 p12/int2/ti1/ti2 p11/int1 p10/int0 p03/si/sb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 reset p73/kr7 p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 7 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 pin identification bias : lcd power supply bias control pcl : programmable clock bp0-bp7 : bit port pto0-pto2 : programmable timer output 0-2 buz : buzzer clock reset : reset input com0-com3 : common output 0-3 s0-s31 : segment output 0-31 ic : internally connected sb0, sb1 : serial bus 0, 1 int0, int1, int4 : external vectored interrupt 0, 1, 4 sck : serial clock int2 : external test input 2 si : serial input kr0-kr7 : key return so : serial output lcdcl : lcd clock sync : lcd synchronization p00-p03 : port 0 ti0-ti2 : timer input 0-2 p10-p13 : port 1 v dd : positive power supply p20-p23 : port 2 v lc0 -v lc2 : lcd power supply 0-2 p30-p33 : port 3 v ss : ground p40-p43 : port 4 x1, x2 : main system clock oscillation 1, 2 p50-p53 : port 5 xt1, xt2 : subsystem clock oscillation 1, 2 p60-p63 : port 6 p70-p73 : port 7 8 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 2. block diagram notes 1. m pd753012a and 753016a have a 14-bit configuration, and m pd753017a has a 15-bit configuration. 2. capacity of the rom depends on the product. ti0/p13 pto0/p20 buz/p23 si/sb1/p03 so/sb0/p02 sck/p01 int0/p10 int1/p11 int2/p12 int4/p00 kr0/p60- kr7/p73 bit seq. buffer (16) interrupt control clocked serial interface watch timer timer/event counter #0 basic interval /watchdog timer intbt intt0 tout0 intcsi tout0 intw f lcd 8 intt1 intt2 tout0 pto1/p21 pto2/p22/pcl ti1/ti2/ p12/int2 timer/event counter #1 timer/event counter #2 program counter note 1 rom note 2 program memory alu decode and control cy sp (8) sbs bank general reg. ram data memory 1024 x 4 bits port0 port1 port2 port3 port4 port5 port6 port7 4 4 4 4 4 4 4 4 p00-p03 p10-p13 p20-p23 p30-p33 p40-p43 p50-p53 p60-p63 p70-p73 s0-s23 s24/bp0- s31/bp7 com0-com3 v lc0 -v lc2 bias lcdcl/p30 sync/p31 lcd controller /driver 24 8 4 3 f lcd reset v ss v dd ic x2 xt2 x1 xt1 pcl/pto2/p22 clock output control clock divider system clock generator stand by control sub main fx/2 n cpu clock f 9 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 3. pin function 3.1 port pins (1/2) pin name i/o alternate function 8-bit after reset i/o circuit function i/o type note 1 p00 input int4 no input p01 sck 10 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 3.1 port pins (2/2) pin name i/o alternate function 8-bit after reset i/o circuit function i/o type note 1 p60 i/o kr0 yes input 11 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 3.2 non-port pins (1/2) pin name i/o alternate function after reset i/o circuit function type note 1 ti0 input p13 inputs external event pulses to the timer/event input -c ti1 p12/int2 counter. ti2 pto0 output p20 timer/event counter output input e-b pto1 p21 pto2 p22/pcl pcl p22/pto2 clock output buz p23 optional frequency output (for buzzer output or system clock trimming) sck i/o p01 serial clock input/output input 12 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 3.2 non-port pins (2/2) pin name i/o alternate function after reset i/o circuit function type note x1 input C C C x2 C C xt1 input C C C xt2 C reset input C system reset input (low level active) C ic C C internally connected. connect directly to v dd .C C v dd C C positive power supply C C v ss C C gnd C C note circuit types enclosed in brackets indicate the schmitt trigger input. crystal/ceramic connection pin for the mainsystem clock oscillation. when inputting the external clock, input the external clock to pin x1, and the inverted phase of the external clock to pin x2. crystal connection pin for the subsystem clock oscillation. when the external clock is used, input the external clock to pin xt1, and the inverted phase of the external clock to pin xt2. pin xt1 can be used as a 1-bit input (test) pin. 13 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 3.3 pin input/output circuits the m pd753017a pin input/output circuits are shown schematically. type a type b type d type e-b type b-c type f-a v dd in p-ch n-ch data output disable n-ch p-ch in out v dd p-ch output disable data p.u.r. enable type d type a in/out v dd p.u.r. enable p.u.r. p-ch in v dd p.u.r. p.u.r. enable p-ch in/out type d type b output disable data p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor schmitt trigger input with hysteresis characteristics cmos standard input buffer push-pull output that can be placed in output high impedance (both p-ch and n-ch off). p.u.r. v dd 14 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 type f-b type h-a type g-a type m-c type g-b type m-d v dd p.u.r. enable p.u.r. p-ch p-ch v dd n-ch output disable (p) data output disable output disable (n) in/out bit port data output disable out type g-a type d seg data v lc0 v lc1 p-ch n-ch out n-ch v lc2 n-ch com or seg data data output disable p.u.r. enable p.u.r. v dd p-ch in/out n-ch p.u.r. : pull-up resistor p.u.r. : pull-up resistor p-ch n-ch n-ch v lc0 v lc1 seg data v lc2 out n-ch p-ch in/out p.u.r. (mask option) data output disable n-ch p-ch input instruction (+13 v withstand voltage) the pull-up resistor operates only when an input instruction is executed (current flows from v dd to the pin when the pin is low). v dd v dd p.u.r. voltage limitation circuit note (+13 v withstand voltage) note 15 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 3.4 recommended connection for unused pins table 3-1. list of recommended connection for unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck connect to v ss or v dd via a resistor individually p02/so/sb0 p03/si/sb1 connect to v ss p10/int0, p11/int1 connect to v ss or v dd p12/ti1/ti2/int2 p13/ti0 p20/pto0 input: connect to v ss or v dd via a resistor individually p21/pto1 output: leave open p22/pto2/pcl p23/buz p30/lcdcl p31/sync p32 p33 p40-p43 input: connect to v ss p50-p53 output: connect to v ss (do not connect a pull-up resistor of mask option) p60/kr0-p63/kr3 input: connect to v ss or v dd via a resistor individually p70/kr4-p73/kr7 output: leave open s0-s23 leave open s24/bp0-s31/bp7 com0-com3 v lc0 -v lc2 connect to v ss bias only if all of v lc0 -v lc2 are unused, connect to v ss . in other cases, leave open. xt1 connect to v ss xt2 note leave open ic connect to v dd directly note when the subsystem clock is not used, set sos.0 to 1 (so as not to use the internal feedback resistor). 16 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 4. switching function between mk i mode and mk ii mode 4.1 differences between mk i mode and mk ii mode the cpu of m pd753017a has the following two modes: mk i and mk ii, either of which can be selected. the mode can be switched by the bit 3 of the stack bank select register (sbs). ? mk i mode: upward compatible with m pd75316b. can be used in the 75xl cpu with a rom capacity of up to 16k bytes. ? mk ii mode: incompatible with m pd75316b. can be used in all the 75xl cpus including those products whose rom capacity is more than 16k bytes. table 4-1. differences between mk i mode and mk ii mode mk i mode mk ii mode program memory (bytes) ? m pd753012a : 12288 ? m pd753012a : 12288 ? m pd753016a, 753017a : 16384 ? m pd753016a : 16384 ? m pd753017a : 24576 number of stack bytes 2 bytes 3 bytes for subroutine instructions bra !addr1 instruction not available available calla !addr1 instruction call !addr instruction 3 machine cycles 4 machine cycles callf !faddr instruction 2 machine cycles 3 machine cycles caution the mk ii mode supports a program area exceeding 16 kbytes for the 75x and 75xl series. therefore, this mode is effective for enhancing software compatibility with products exceeding 16 kbytes. when the mk ii mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the mk i mode. when the call !addr and callf !faddr instructions are used, the machine cycle becomes longer by one machine cycle. therefore, use the mk i mode if the ram efficiency and processing performance are more important than software compatibility. 17 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 caution since sbs. 3 is set to 1 after a reset signal is generated, the cpu operates in the mk i mode. when executing an instruction in the mk ii mode, set sbs. 3 to 0 to select the mk ii mode. 4.2 setting method of stack bank select register (sbs) switching between the mk i mode and mk ii mode can be done by the stack bank select register (sbs). figure 4-1 shows the format. the sbs is set by a 4-bit memory manipulation instruction. when using the mk i mode, the sbs must be initialized to 10xxb note at the beginning of a program. when using the mk ii mode, it must be initialized to 00xxb note . note set the desired value in the xx positions. figure 4-1. stack bank select register format sbs3 sbs2 sbs1 sbs0 3210 symbol sbs address f84h 00 01 10 11 0 1 0 memory bank 0 memory bank 1 memory bank 2 memory bank 3 be sure to set bit 2 to 0. stack area specification mk ii mode mk i mode mode switching specification 18 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 5. memory configuration ? program memory (rom) ............... 12288 8 bits ( m pd753012a) ............... 16384 8 bits ( m pd753016a) ............... 24576 8 bits ( m pd753017a) addresses 0000h and 0001h vector table wherein the program start address and the values set for the rbe and mbe at the time a reset signal is generated are written. reset start is possible from any address. addresses 0002h to 000dh vector table wherein the program start address and the values set for the rbe and mbe by each vectored interrupt are written. interrupt processing can start from any address. addresses 0020h to 007fh table area referenced by the geti instruction note . note the geti instruction realizes a 1-byte instruction on behalf of any 2-byte/3-byte instruction, or two 1- byte instructions. it is used to decrease the number of program steps. ? data memory (ram) data area 1024 words 4 bits (000h to 3ffh) peripheral hardware area128 4 bits (f80h to fffh) 19 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 5-1. program memory map (1/3) (a) m pd753012a 0000h rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe internal reset start address (high-order 6 bits) (iow-order 8 bits) (high-order 6 bits) (iow-order 8 bits) (high-order 6 bits) (iow-order 8 bits) (high-order 6 bits) (iow-order 8 bits) (high-order 6 bits) (iow-order 8 bits) (high-order 6 bits) (iow-order 8 bits) (high-order 6 bits) (iow-order 8 bits) intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address intt1, intt2 start address geti instruction reference table callf !faddr instruction entry address brcb !caddr instruction branch address brcb !caddr instruction branch address branch destination address and subroutine entry address when geti instruction is executed branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction call !addr instruction subroutine entry address br $addr instruction relative branch address (?5 to ?, +2 to +16) 765 0 0002h 0004h 0006h 0008h 000ah 000ch 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh brcb !caddr instruction branch address mbe internal reset start address intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address intt1, intt2 start address note can be used only in the mk ii mode. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of pc by executing the br pcde, br pcxa instruction. 20 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 5-1. program memory map (2/3) (b) m pd753016a note can be used only in the mk ii mode. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of pc by executing the br pcde, br pcxa instruction. mbe rbe internal reset start address (high-order 6 bits) mbe rbe intbt/int4 start address (high-order 6 bits) mbe rbe int0 start address (high-order 6 bits) mbe rbe int1 start address (high-order 6 bits) mbe rbe intcsi start address (high-order 6 bits) mbe rbe intt0 start address (high-order 6 bits) mbe rbe intt1,intt2 start address (high-order 6 bits) (iow-order 8 bits) (iow-order 8 bits) (iow-order 8 bits) (iow-order 8 bits) (iow-order 8 bits) (iow-order 8 bits) geti instruction reference table 765 0 callf !faddr instruction entry address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction brcb !caddr instruction branch address call !addr instruction subroutine entry address br $addr instruction relative branch address (?5 to ?, +2 to +16) branch destination address and subroutine entry address when geti instruction is executed brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address (iow-order 8 bits) 0000h 0002h 0004h 0006h 0008h 000ah 000ch 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3fffh intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address internal reset start address intt1,intt2 start address 21 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 5-1. program memory map (3/3) (c) m pd753017a mbe rbe internal reset start address (high-order 6 bits) mbe rbe intbt/int4 start address (high-order 6 bits) mbe rbe int0 start address (high-order 6 bits) mbe rbe int1 start address (high-order 6 bits) mbe rbe intcsi start address (high-order 6 bits) mbe rbe intt0 start address (high-order 6 bits) mbe rbe intt1,intt2 start address (high-order 6 bits) (iow-order 8 bits) (iow-order 8 bits) (iow-order 8 bits) (iow-order 8 bits) (iow-order 8 bits) (iow-order 8 bits) geti instruction reference table callf !faddr instruction entry address brcb !caddr instruction branch address brcb !caddr instruction branch address 765 0 brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address br !addr instruction branch address call !addr instruction branch address geti instruction branch/call address branch address of br bcde, br bcxa, bra !addr1 note or calla !addr1 note instruction br $addr1 instruction relative branch address (?5 to ?, +2 to +16) (iow-order 8 bits) 0000h 0002h 0004h 0006h 0008h 000ah 000ch 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3fffh 4000h 4fffh 5000h 5fffh internal reset start address intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address intt1,intt2 start address note can be used only in the mk ii mode. caution the interrupt vector start address shown above consists of 14 bits. set it in 16k space (0000h- 3fffh). remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of pc by executing the br pcde, br pcxa instruction. 22 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 5-2. data memory map note for stack area, one memory bank can be selected among memory banks 0 to 3. data area static ram (1024 4) stack area note general purpose register area display data memory peripheral hardware area (32 4) 256 4 (224 4) 256 4 (224 4) (32 4) 256 4 256 4 not incorporated 128 4 15 3 2 1 0 data memory memory bank 000h 01fh 020h 0ffh 100h 1dfh 1e0h 1ffh 200h 2ffh 300h 3ffh f80h fffh 23 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6. peripheral hardware functions 6.1 digital input/output ports there are four types of i/o ports as follows. cmos input (port0, 1) : 8 cmos input/output (port2, 3, 6, 7) : 16 n-channel open-drain input/output (port4, 5) : 8 bit port output (bp0-bp7) : 8 total 40 table 6-1. types and features of digital ports port (pin name) function operation and features remarks port0 4-bit input when the serial interface function is used, the alternate also used for the int4, (p00-p03) function pins function as output ports depending on the sck, so/sb0, si/sb1 pins. operation mode. port1 input-only port also used for the int0- (p10-p13) int2 and ti0-ti2 pins. port2 4-bit i/o can be set to input mode or output mode in 4-bit units. also used for the pto0- (p20-p23) pto2, pcl, buz pins. port3 can be set to input mode or output mode in 1/4-bit also used for the lcdcl, (p30-p33) units. sync pins. port4 4-bit i/o can be set to input mode ports 4 and 5 are paired on-chip pull-up resistor can (p40-p43) (n-channel or output mode in 4-bit and data can be input/ be specified bit-wise by open-drain, units. output in 8-bit units. mask option. port5 13 v (p50-p53) withstanding) port6 4-bit i/o can be set to input mode ports 6 and 7 are paired also used for the kr0-kr3 (p60-p63) or output mode in 1/4-bit and data can be input/ pins. units. output in 8-bit units. port7 can be set to input mode also used for the kr4-kr7 (p70-p73) or output mode in 4-bit pins. units. bp0-bp7 1-bit output outputs data bit-wise. can be switched to lcd drive segment output s24-s31 by software. 24 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.2 clock generator operation of the clock generator is determined by the processor clock control register (pcc) and system clock control register (scc). the two clocks, the main system clock and subsystem clock, are available. the instruction excution time can be altered. ? 0.95 m s, 1.91 m s, 3.81 m s, 15.3 m s (main system clock : at 4.19 mhz operation) ? 0.67 m s, 1.33 m s, 2.67 m s, 10.7 m s (main system clock : at 6.0 mhz operation) ? 122 m s (subsystem clock : at 32.768 khz operation) figure 6-1. clock generator block diagram note instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. one clock cycle (t cy ) of f equal to one machine cycle of the instruction. v dd v dd xt1 x1 xt2 x2 f xt f x subsystem clock oscillator main system clock oscillator 4 halt note stop note wm.3 scc scc3 scc0 pcc0 pcc1 pcc2 pcc3 pcc2, pcc3 clear stop f/f q s r oscillation stop halt f/f s r wait release signal from bt reset signal standby release signal from interrupt control circuit ?cpu ?int0 noise elimination circuit ?clock output circuit f 1/4 divider 1/1 to 1/4096 divider 1/2 1/4 1/16 ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?lcd controller/driver ?int0 noise elimination circuit ?clock output circuit lcd controller/driver watch timer pcc q selector selector internal bus 25 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.3 subsystem clock oscillator control functions the m pd753017a subsystem clock oscillator has the following two control functions. ? selects by software whether an internal feedback resistor is to be used or not note . ? reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (v dd 3 2.7 v). note when the subsystem clock is not used, set sos.0 to 1 (so as not to use the internal feedback resistor) by software, connect xt1 to v ss , and open xt2. this makes it possible to reduce the current consumption in the subsystem clock oscillator. the above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (sos). (see figure 6-2.) figure 6-2. subsystem clock oscillator feedback resistor sos.0 sos.1 xt1 xt2 inverter v dd 26 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.4 clock output circuit the clock output circuit is provided to output the clock pulses from the p22/pto2/pcl pin to the application of remote control wave outputs and peripheral lsis. ? clock output (pcl) : f , 524, 262, 65.5 khz (at 4.19 mhz operation) f , 750, 375, 93.8 khz (at 6.0 mhz operation) figure 6-3. clock output circuit block diagram remark special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. from clock generator f f x /2 3 f x /2 4 f x /2 6 selector clom3 0 clom1 clom0 4 clom p22 output latch port 2 i/o mode specification bit port2.2 bit 2 of pmgb internal bus output buffer pcl/pto2/p22 selector from timer/event counter (channel 2) 27 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.5 basic interval timer/watchdog timer the basic interval timer/watchdog timer has the following functions. ? interval timer operation to generate a reference time interrupt ? watchdog timer operation to detect a runaway of program and reset the cpu ? selects and counts the wait time when the standby mode is released ? reads the contents of counting figure 6-4. basic interval timer/watchdog timer block diagram note instruction execution from clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx btm3 btm2 btm1 btm0 btm 4 set1 note internal bus 8 basic interval timer (8-bit frequency divider) clear bt wait release signal when standby is released. set clear 3 wdtm set1 note internal reset signal vectored interrupt request signal bt interrupt request flag irqbt 1 28 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.6 watch timer the m pd753017a has one channel of watch timer. the watch timer has the following functions. ? sets the test flag (irqw) with 0.5 sec interval. the standby mode can be released by the irqw. ? 0.5 sec interval can be created by both the main system clock (4.19 mhz) and subsystem clock (32.768 khz). ? convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. ? outputs the frequencies (2.048, 4.096, 32.768 khz) to the p23/buz pin, usable for buzzer and trimming of system clock oscillation frequencies. ? clears the frequency divider to make the clock start with zero seconds. figure 6-5. watch timer block diagram from clock generator selector f x 128 (32.768 khz) f xt (32.768 khz) f w (32.768 khz) divider 4 khz 2 khz f w 2 3 f w 2 4 clear selector f w 2 7 f w 2 6 (512 hz : 1.95 ms) (256 hz : 3.91 ms) f w 2 14 selector 2 hz 0.5 sec irqw set signal intw f lcd output buffer pmgb bit 2 port2.3 wm wm7 0 wm5 wm4 wm3 wm2 wm1 wm0 p23 output latch port 2 input/ output mode 8 internal bus bit test instruction p23/buz the values enclosed in parentheses are applied when f x = 4.19 mhz and f xt = 32.768 khz. 29 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.7 timer/event counter the m pd753017a has three channels of timer/event counter. the timer/event counter has the following functions. ? programmable interval timer operation ? square wave output of any frequency to the pton pin (n = 0, 1) ? event counter operation ? divides the frequency of signal input via the tin pin to 1-nth of the original signal and outputs the divided frequency to the pton pin (frequency division operation). ? supplies the shift clock to the serial interface circuit (channel 0 only). ? calls the count value. the timer/event counter operates in the following four modes as set by the mode register. table 6-2. operation modes of timer/event counter channel channel 0 channel 1 channel 2 mode 8-bit timer/event counter mode yes yes yes gate control function no note no yes pwm pulse generator mode no no yes 16-bit timer/event counter mode no yes gate control function no note yes carrier generator mode no yes note used for gate control signal generation 30 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 6-6. timer/event counter block diagram (channel 0) port1.3 input buffer ti0 f x /2 4 f x /2 6 f x /2 8 f x /2 10 mpx tm06 tm05 tm04 tm03 tm02 8 8 8 set1 tm0 modulo register (8) comparator (8) count register (8) tmod0 t0 cp timer operation start clear match tout0 tout f/f reset to enable flag p20 output latch port 2 input/output mode toe0 port2.0 pmgb bit 2 to serial interface p20/pto0 intt0 irqt0 set signal reset irqt0 clear signal to timer/event counter (channel 2) internal bus output buffer from clock generator 88 31 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 6-7. timer/event counter block diagram (channel 1) port1.2 input buffer ti1/ti2/p12/int2 timer/event counter output (channel 2) from clock generator f x /2 5 f x /2 6 f x /2 8 f x /2 10 f x /2 12 mpx tm16 tm15 tm14 tm13 tm12 tm11 tm10 tm1 decoder 16-bit timer/event counter mode cp timer operation start selector clear 8 8 8 8 modulo register (8) comparator (8) count register (8) timer/event counter match signal (channel 2) (when 16-bit timer/event counter mode) timer/event counter comparator (channel 2) (when 16-bit timer/event counter mode) timer/event counter reload signal (channel 2) t1 tmod1 match tout f/f reset t1 enable flag p21 output latch port 2 input/output mode intt1 irqt1 set signal irqt1 clear signal reset toe1 port2.1 pmgb.2 p21/pto1 output buffer internal bus 32 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 6-8. timer/event counter block diagram (channel 2) port1.2 input buffer ti1/ti2/ p12/int2 from clock generator f x f x /2 f x /2 4 f x /2 6 f x /2 8 f x /2 10 mpx tm25 tm26 tm24 tm23 tm22 tm21 tm20 tm2 8 tc2 decoder modulo register for high level period setup (8) modulo register (8) tgce toe2 remc nrzb nrz reload mpx (8) comparator (8) count register (8) 8 8 clear 16-bit timer/event counter mode timer operation start timer/event counter match signal (channel 1) (when 16-bit timer/event counter mode) timer/event counter clear signal (channel 1) (when 16-bit timer/event counter mode) timer/event counter match signal (channel 1) (when carrier generator mode) tout f/f overflow carrier generator mode port2.2 pmgb.2 p22 output latch port 2 input/output output buffer p22/pcl/pto2 timer/event counter clock input (channel 1) intt2 irqt2 set signal irqt2 clear signal reset t2 tmod2 tmod2h internal bus cp timer event counter tout f/f (channel 0) reset 88 selector selector match selector from clock output circuit 88 8 33 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.8 serial interface the m pd753017a is provided with an 8-bit clocked serial interface. this serial interface operates in the following four modes: operation stop mode 3-wire serial i/o mode 2-wire serial i/o mode sbi mode 34 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 6-9. serial interface block diagram internal bus 8 8 8 8/4 bit manipulation bit test sbic slave address register (sva) address comparator shift register (sio) (8) (8) (8) relt cmdt so latch set clr dq csim p03/si/sb1 p02/so/sb0 p01/sck p01 output iatch bus release/ command/ acknowledge detection circuit reld cmdd ackd ackt serial clock counter serial clock control circuit serial clock selector intcsi control circuit acke bsye busy/ acknowledge output circuit intcsi irqcsi set signal f x /2 3 f x /2 4 f x /2 6 tout0 (from timer/ event counter 0) external sck bit test match signal selector selector 35 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.9 lcd controller/driver the m pd753017a incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the lcd panel directly. the m pd753017a lcd controller/driver functions are as follows: ? display data memory is read automatically by dma operation and segment and common signals are generated. ? display mode can be selected from among the following five: 1 ? static 2 ? 1/2 duty (time multiplexing by 2), 1/2 bias 3 ? 1/3 duty (time multiplexing by 3), 1/2 bias 4 ? 1/3 duty (time multiplexing by 3), 1/3 bias 5 ? 1/4 duty (time multiplexing by 4), 1/3 bias ? a frame frequency can be selected from among four in each display mode. ? a maximum of 32 segment signal output pins (s0-s31) and four common signal output pins (com0-com3). ? the segment signal output pins (s24-s27 and s28-s31) can be changed to the output ports in 4-pin units. ? split-resistor can be incorporated to supply lcd drive power (mask option). various bias methods and lcd drive voltages can be applicable. when display is off, current flow to the split resistor is cut. ? display data memory not used for display can be used for normal data memory. ? it can also operate by using the subsystem clock. 36 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 6-10. lcd controller/driver block diagram internal bus 4 4 display data memory multi- plexer timing controller 1ffh 32 1 0 1feh 32 1 0 1f9h 32 1 0 1f8h 32 1 0 1e0h 32 1 0 32 1 0 32 1 0 32 1 0 32 1 0 32 1 0 display mode register display control register port 3 output latch port mode register group a f lcd selector s31/bp7 s30/bp6 s24/bp0 s23 s0 com3 com2 com1 com0 v lc2 v lc1 v lc0 p31/ sync p30/ lcdcl lcd drive voltage control common driver segment driver lcd drive mode changer 10 10 48 8 37 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 6.10 bit sequential buffer 16 bits the bit sequential buffer (bsb) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. figure 6-11. bit sequential buffer format address bit symbol l register l = fh l = ch l = bh l = 8h l = 7h l = 4h l = 3h l = 0h decs l incs l bsb3 bsb2 bsb1 bsb0 3210321032103210 fc3h fc2h fc1h fc0h remarks 1. in the pmem.@l addressing, the specified bit moves corresponding to the l register. 2. in the pmem.@l addressing, the bsb can be manipulated regardless of mbe/mbs specification. 38 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 7. interrupt function and test function m pd753017a has eight types of interrupt sources and two types of test sources. among the test sources, int2 is provided with two testable inputs for edge detection. m pd753017a has the following functions in the interrupt control circuit. (1) interrupt function ? vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (iexxx) and interrupt master enable flag (ime). ? can set any interrupt start address. ? nesting interrupts wherein the order of priority can be specified by the interrupt priority select register (ips). ? test function of interrupt request flag (irqxxx). an interrupt generated can be checked by software. ? release the standby mode. a release interrupt can be selected by the interrupt enable flag. (2) test function ? test request flag (irqxxx) generation can be checked by software. ? release the standby mode. the test source to be released can be selected by the test enable flag. 39 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 figure 7-1. interrupt control circuit block diagram note noise elimination circuit (standby release is disabled when noise elimination circuit is selected.) internal bus interrupt enable flag (ie ) irqbt irq4 irq0 irq1 irqcsi irqt0 irqt1 irqt2 irqw irq2 intcsi intt0 intt1 intt2 intw both edge detector edge detector edge detector selec- tor int4/p00 int0/p10 int1/p11 int2/p12 kr0/p60 kr3/p63 rising edge detector falling edge detector selec- tor im2 standby release signal priority control circuit vector table address generator decoder ime ips ist0 vrqn note im2 im1 im0 214 intbt ist1 40 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 8. standby function in order to save power consumption while a program is in a standby mode, two types of standby modes (stop mode and halt mode) are provided for the m pd753017a. table 8-1. operation status in standby mode stop mode halt mode set instruction stop instruction halt instruction system clock when set settable only when the main system settable both by the main system clock is used. clock and subsystem clock. operation clock generator only the main system clock stops only the cpu clock f halts (oscillation status oscillation. continues). basic interval timer/ operation stops operation. (the irqbt is set in the watchdog timer reference interval.) note 1 serial interface operable only when an external sck operable note 1 input is selected as the serial clock. timer/event counter operable only when a signal input to the operable note 1 ti0-ti2 pins is specified as the count clock. watch timer operable when f xt is selected as the operable count clock. lcd controller/driver operable only when f xt is selected as operable the lcdcl. external interrupt the int1, 2, and 4 are operable. only the int0 is not operated. note 2 cpu the operation stops. release signals ? interrupt request signal sent from the operable hardware enabled by the interrupt enable flag. ? test request signal sent from the test source enabled by the test enable flag. ? reset input notes 1. cannot operate only when the main system clock stops. 2. can operate only when the noise elimination circuit is not used (im02 = 1) by bit 2 of the edge detection mode register (im0). 41 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 9. reset function there are two reset inputs: external reset signal (reset) and reset signal sent from the basic interval timer/ watchdog timer. when either one of the reset signals are input, an internal reset signal is generated. figure 9- 1 shows the circuit diagram of the above two inputs. figure 9-1. configuration of reset function the m pd753017a is set by the reset signal generated and each hardware is initialized as listed in table 9-1. figure 9-2 shows the timing chart of the reset operation. figure 9-2. reset operation by reset signal generation note the following two times can be selected by the mask option. 2 17 /f x (21.8 ms : at 6.0 mhz operation, 31.3 ms : at 4.19 mhz operation) 2 15 /f x (5.46 ms : at 6.0 mhz operation, 7.81 ms : at 4.19 mhz operation) reset internal reset signal reset signal sent from the basic interval timer/watchdog timer wdtm internal bus operation mode or standby mode wait note reset signal generated operation mode halt mode internal reset operation 42 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 table 9-1. status of each hardware after reset (1/2) hardware reset signal generation reset signal generation in standby mode in operation program counter (pc) sets the low-order 6 bits of sets the low-order 6 bits of program memorys address program memorys address 0000h to the pc13-pc8 and the 0000h to the pc13-pc8 and the contents of address 0001h to contents of address 0001h to the pc7-pc0. resets the pc14 the pc7-pc0. resets the pc14 of the m pd753017a to 0. of the m pd753017a to 0. psw carry flag (cy) held undefined skip flag (sk0-sk2) 0 0 interrupt status flag (ist0) 0 0 bank enable flag (mbe, rbe) sets the bit 6 of program sets the bit 6 of program memorys address 0000h to memorys address 0000h to the rbe and bit 7 to the mbe. the rbe and bit 7 to the mbe. stack pointer (sp) undefined undefined stack bank select register (sbs) 1000b 1000b data memory (ram) held undefined general-purpose register (x, a, h, l, d, e, b, c) held undefined bank select register (mbs, rbs) 0, 0 0, 0 basic interval counter (bt) undefined undefined timer/ mode register (btm) 0 0 watchdog timer watchdog timer enable flag (wdtm) 00 timer/event counter (t0) 0 0 counter (t0) modulo register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 timer/event counter (t1) 0 0 counter (t1) modulo register (tmod1) ffh ffh mode register (tm1) 0 0 toe1, tout f/f 0, 0 0, 0 timer/event counter (t2) 0 0 counter (t2) modulo register (tmod2) ffh ffh high level period setting modulo ffh ffh register (tmod2h) mode register (tm2) 0 0 toe2, tout f/f 0, 0 0, 0 remc, nrz, nrzb 0, 0, 0 0, 0, 0 tge 0 0 watch timer mode register (wm) 0 0 43 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 table 9-1. status of each hardware after reset (2/2) hardware reset signal generation reset signal generation in standby mode in operation serial interface shift register (sio) held undefined operation mode register (csim) 0 0 sbi control register (sbic) 0 0 slave address register (sva) held undefined clock generator, processor clock control register (pcc) 0 0 clock output system clock control register (scc) 0 0 circuit clock output mode register (clom) 0 0 sub-oscillator control register (sos) 0 0 lcd controller/ display mode register (lcdm) 0 0 driver display control register (lcdc) 0 0 interrupt interrupt request flag (irqxxx) reset (0) reset (0) function interrupt enable flag (iexxx) 0 0 interrupt master enable flag (ime) 0 0 int0, 1, 2 mode registers (im0, im1, im2) 0, 0, 0 0, 0, 0 interrupt priority selection register (ips) 00 digital port output buffer off off output latch cleared (0) cleared (0) i/o mode registers (pmga, pmgb) 0 0 pull-up resistor specification register (poga) 00 bit sequential buffer (bsb0-bsb3) held undefined 44 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 10. mask option the m pd753017a has the following mask options. p40-p43, p50-p53 mask options on-chip pull-up resistors can be connected. <1> on-chip pull-up resistors are specifiable bit-wise. <2> on-chip pull-up resistors are not specifiable. v lc0 -v lc2 pins, bias pin mask option on-chip split resistor for lcd drive can be connected. <1> split resistor is not connected. <2> four 10 k w (typ.) split resistors are connected at the same time. <3> four 100 k w (typ.) split resistors are connected at the same time. standby function mask option wait times can be selected by a reset signal. <1> 2 17 /f x (21.8 ms : at f x = 6.0 mhz, 31.3 ms : at f x = 4.19 mhz) <2> 2 15 /f x (5.46 ms : at f x = 6.0 mhz, 7.81 ms : at f x = 4.19 mhz) subsystem clock mask option use of the internal feedback resistor can be selected. <1> internal feedback resistor can be used. (switched on/off via software) <2> internal feedback resistor cannot be used. (switched out in hardware) 45 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 11. instruction set (1) expression formats and description methods of operands the operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. for details, refer to ra75x assembler package users manuallanguage (u12385e) . if there are several elements, one of them is selected. capital letters and the + and C symbols are key words and are described as they are. for immediate data, appropriate numbers and labels are described. instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described. however, there are restrictions in the labels that can be described for fmem and pmem. for details, see users manual. expression description method format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr 0000h-2fffh immediate data or label ( m pd753012a) 0000h-3fffh immediate data or label ( m pd753016a, 753017a) addr1 0000h-5fffh immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (where bit0 = 0) or label portn port0-port7 iexxx iebt, iet0-iet2, ie0-ie2, ie4, iecsi, iew rbn rb0-rb3 mbn mb0, mb1, mb2, mb3, mb15 note mem can be only used even address in 8-bit data processing. 46 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 (2) legend in explanation of operation a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : xa register pair; 8-bit accumulator bc : bc register pair de : de register pair hl : hl register pair xa' : xa' expanded register pair bc' : bc' expanded register pair de' : de' expanded register pair hl' : hl' expanded register pair pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0-7) ime : interrupt master enable flag ips : interrupt priority selection register iexxx : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : separation between address and bit (xx) : the contents addressed by xx xxh : hexadecimal data 47 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 (3) explanation of symbols under addressing area column *1 mb = mbe?mbs (mbs = 0-3, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (000h-07fh) mb = 15 (f80h-fffh) data memory addressing mbe = 1 : mb = mbs (mbs = 0-3, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 m pd753012a addr = 0000h-2fffh m pd753016a addr = 0000h-3fffh 753017a *7 m pd753012a addr = (current pc) C 15 to (current pc) C 1 753016a (current pc) + 2 to (current pc) + 16 753017a (in mk i mode) m pd753017a addr1 = (current pc) C 15 to (current pc) C 1 (in mk ii mode) (current pc) + 2 to (current pc) + 16 *8 m pd753012a caddr = 0000h-0fffh (pc 13, 12 = 00b) or 1000h-1fffh (pc 13, 12 = 01b) or 2000h-2fffh (pc 13, 12 = 10b) m pd753016a caddr = 0000h-0fffh (pc 13, 12 = 00b) or 1000h-1fffh (pc 13, 12 = 01b) or program memory addressing 2000h-2fffh (pc 13, 12 = 10b) or 3000h-3fffh (pc 13, 12 = 11b) m pd753017a caddr = 0000h-0fffh (pc 14, 13, 12 = 000b) or 1000h-1fffh (pc 14, 13, 12 = 001b) or 2000h-2fffh (pc 14, 13, 12 = 010b) or 3000h-3fffh (pc 14, 13, 12 = 011b) or 4000h-4fffh (pc 14, 13, 12 = 100b) or 5000h-5fffh (pc 14, 13, 12 = 101b) *9 faddr = 0000h-07ffh *10 taddr = 0020h-007fh *11 m pd753012a addr1 = 0000h-2fffh m pd753016a addr1 = 0000h-3fffh m pd753017a addr1 = 0000h-5fffh remarks 1. mb indicates memory bank that can be accessed. 2. in *2, mb = 0 independently of how mbe and mbs are set. 3. in *4 and *5, mb = 15 independently of how mbe and mbs are set. 4. *6 to *11 indicate the areas that can be addressed. 48 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 (4) explanation of number of machine cycles column s denotes the number of machine cycles required by skip operation when a skip instruction is executed. the value of s varies as follows. ? when no skip is made: s = 0 ? when the skipped instruction is a 1- or 2-byte instruction: s = 1 ? when the skipped instruction is a 3-byte instruction note : s = 2 note 3-byte instruction: br !addr, bra !addr1, call !addr or calla !addr1 instruction caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle of cpu clock f (= t cy ); time can be selected from among four types by setting pcc. 49 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area transfer mov a, #n4 1 1 a ? n4 string effect a reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 string effect a hl, #n8 2 2 hl ? n8 string effect b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2+s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 @hl, a 1 1 (hl) ? a*1 @hl, xa 2 2 (hl) ? xa *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 mem, a 2 2 (mem) ? a*3 mem, xa 2 2 (mem) ? xa *3 a, reg1 2 2 a ? reg1 xa, rp' 2 2 xa ? rp' reg1, a 2 2 reg1 ? a rp'1, xa 2 2 rp'1 ? xa xch a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2+s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp' 2 2 xa ? rp' 50 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area table movt note 1 xa, @pcde 1 3 xa ? (pc 13C8 +de) rom reference l m pd753017a xa ? (pc 14C8 +de) rom xa, @pcxa 1 3 xa ? (pc 13C8 +xa) rom l m pd753017a xa ? (pc 14C8 +xa) rom xa, @bcde note 2 1 3 xa ? (b 1,0 +cde) rom *6 l m pd753017a *11 xa ? (b 2C0 +cde) rom xa, @bcxa note 2 1 3 xa ? (b 1,0 +cxa) rom *6 l m pd753017a *11 xa ? (b 2C0 +cxa) rom bit transfer mov1 cy, fmem.bit 2 2 cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) ? cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) ? cy *1 operation adds a, #n4 1 1+s a ? a+n4 carry xa, #n8 2 2+s xa ? xa+n8 carry a, @hl 1 1+s a ? a+(hl) *1 carry xa, rp' 2 2+s xa ? xa+rp' carry rp'1, xa 2 2+s rp'1 ? rp'1+xa carry addc a, @hl 1 1 a, cy ? a+(hl)+cy *1 xa, rp' 2 2 xa, cy ? xa+rp'+cy rp'1, xa 2 2 rp'1, cy ? rp'1+xa+cy subs a, @hl 1 1+s a ? aC(hl) *1 borrow xa, rp' 2 2+s xa ? xaCrp' borrow rp'1, xa 2 2+s rp'1 ? rp'1Cxa borrow subc a, @hl 1 1 a, cy ? aC(hl)Ccy *1 xa, rp' 2 2 xa, cy ? xaCrp'Ccy rp'1, xa 2 2 rp'1, cy ? rp'1CxaCcy notes 1. the above operations in the shaded boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 2. only the following bits are valid for the b register. m pd753012a, 753016a : low-order 2 bits m pd753017a : low-order 3 bits remark when the m pd753017a is set in the mk i mode, pc 14 is fixed to 0. 51 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area operation and a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa or a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa xor a, #n4 2 2 a ? a v n4 a, @hl 1 1 a ? a v (hl) *1 xa, rp' 2 2 xa ? xa v rp' rp'1, xa 2 2 rp'1 ? rp'1 v xa accumulator rorc a 1 1 cy ? a 0 , a 3 ? cy, a nC1 ? a n manipulation not a 2 2 a ? a increment incs reg 1 1+s reg ? reg+1 reg = 0 and decrement rp1 1 1+s rp1 ? rp1+1 rp1 = 00h @hl 2 2+s (hl) ? (hl)+1 *1 (hl) = 0 mem 2 2+s (mem) ? (mem)+1 *3 (mem) = 0 decs reg 1 1+s reg ? regC1 reg = fh rp' 2 2+s rp' ? rp'C1 rp' = ffh comparison ske reg, #n4 2 2+s skip if reg = n4 reg = n4 @hl, #n4 2 2+s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1+s skip if a = (hl) *1 a = (hl) xa, @hl 2 2+s skip if xa = (hl) *1 xa = (hl) a, reg 2 2+s skip if a = reg a = reg xa, rp' 2 2+s skip if xa = rp' xa = rp' carry flag set1 cy 1 1 cy ? 1 manipulation clr1 cy 1 1 cy ? 0 skt cy 1 1+s skip if cy = 1 cy = 1 not1 cy 1 1 cy ? cy 52 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area memory bit set1 mem.bit 2 2 (mem.bit) ? 1*3 manipulation fmem.bit 2 2 *4 pmem.@l 2 2 *5 @h+mem.bit 2 2 *1 clr1 mem.bit 2 2 *3 fmem.bit 2 2 *4 pmem.@l 2 2 *5 @h+mem.bit 2 2 *1 skt mem.bit 2 2+s skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+s skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=1 *1 (@h+mem.bit)=1 skf mem.bit 2 2+s skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+s skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=0 *5 (pmem.@l)=0 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=0 *1 (@h+mem.bit)=0 sktclr fmem.bit 2 2+s skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 and clear *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=1 and clear *1 (@h+mem.bit)=1 and1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 or1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 xor1 cy, fmem.bit 2 2 cy ? cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy v (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy v (h+mem 3C0 .bit) *1 (fmem.bit) ? 1 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 1 (h+mem 3C0 .bit) ? 1 (mem.bit) ? 0 (fmem.bit) ? 0 (pmem 7-2 +l 3-2 .bit(l 1-0 )) ? 0 (h+mem 3-0 .bit) ? 0 53 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br note 1 addr C C pc 13C0 ? addr *6 select appropriate instruction from among the following instructions according to the assembler being used. br !addr brcb !caddr br $addr addr1 C C l m pd753012a, 753016a *11 pc 13C0 ? addr1 select appropriate instruction from among the following instructions according to the assembler being used. br !addr bra !addr1 brcb !caddr br $addr1 l m pd753017a pc 14C0 ? addr1 select appropriate instruction from among the following instructions according to the assembler being used. br !addr bra !addr1 brcb !caddr br $addr1 !addr 3 3 pc 13C0 ? addr *6 l m pd753017a pc 14 ? 0, pc 13C0 ? addr $addr 1 2 pc 13C0 ? addr *7 $addr1 1 2 l m pd753017a pc 14C0 ? addr1 pcde 2 3 pc 13C0 ? pc 13C8 +de l m pd753017a pc 14C0 ? pc 14C8 +de pcxa 2 3 pc 13C0 ? pc 13C8 +xa l m pd753017a pc 14C0 ? pc 14C8 +xa bcde note 2 23pc 13C0 ? bcde *6 l m pd753017a *11 pc 14C0 ? bcde bcxa note 2 23pc 13C0 ? bcxa *6 l m pd753017a *11 pc 14C0 ? bcxa notes 1. the above operations in the shaded boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 2. only the following bits are valid for the b register. m pd753012a, 753016a : low-order 2 bits m pd753017a : low-order 3 bits remark when the m pd753017a is set in the mk i mode, pc 14 is fixed to 0. 54 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch bra note !addr 3 3 l m pd753012a, 753016a *6 pc 13C0 ? addr !addr1 3 3 l m pd753017a *11 pc 14C0 ? addr1 brcb note !caddr 2 2 pc 13C0 ? pc 13,12 +caddr 11-0 *8 l m pd753017a pc 14C0 ? pc 14,13,12 +caddr 11C0 subroutine calla note !addr 3 3 l m pd753012a, 753016a *6 stack control (spC6)(spC3)(spC4) ? pc 11C0 (spC5) ? 0, 0, pc 13, 12 (spC2) ? , , mbe, rbe pc 13C0 ? addr, sp ? spC6 !addr1 3 3 l m pd753017a *11 (spC6)(spC3)(spC4) ? pc 11C0 (spC5) ? 0, pc 14, 13, 12 (spC2) ? , , mbe, rbe pc 14C0 ? addr1, sp ? spC6 call note !addr 3 3 (spC4)(spC1)(spC2) ? pc 11C0 *6 (spC3) ? mbe, rbe, pc 13 , pc 12 pc 13C0 ? addr, sp ? spC4 4 l m pd753012a, 753016a (spC6)(spC3)(spC4) ? pc 11C0 (spC5) ? 0, 0, pc 13, 12 (spC2) ? , , mbe, rbe pc 13C0 ? addr, sp ? spC6 4 l m pd753017a (spC6)(spC3)(spC4) ? pc 11C0 (spC5) ? 0, pc 14, 13, 12 (spC2) ? , , mbe, rbe pc 14 ? 0, pc 13C0 ? addr, sp ? spC6 callf note !faddr 2 2 (spC4)(spC1)(spC2) ? pc 11C0 *9 (spC3) ? mbe, rbe, pc 13 , pc 12 pc 13C0 ? 000+faddr, sp ? spC4 3 l m pd753012a, 753016a (spC6)(spC3)(spC4) ? pc 11C0 (spC5) ? 0, 0, pc 13, 12 (spC2) ? , , mbe, rbe pc 13C0 ? 000+faddr, sp ? spC6 3 l m pd753017a (spC6)(spC3)(spC4) ? pc 11C0 (spC5) ? 0, pc 14, 13, 12 (spC2) ? , , mbe, rbe pc 14C0 ? 0000+faddr, sp ? spC6 note the above operations in the shaded boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. remark when the m pd753017a is set in the mk i mode, pc 14 is fixed to 0. 55 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine ret note 1 3 mbe, rbe, pc 13 , pc 12 ? (sp+1) stack control pc 11C0 ? (sp)(sp+3)(sp+2), sp ? sp+4 l m pd753012a, 753016a , , mbe, rbe ? (sp+4) 0, 0, pc 13 , pc 12 ? (sp+1) pc 11C0 ? (sp)(sp+3)(sp+2), sp ? sp+6 l m pd753017a , , mbe, rbe ? (sp+4) 0, pc 14 , pc 13 , pc 12 ? (sp+1) pc 11C0 ? (sp)(sp+3)(sp+2), sp ? sp+6 rets note 1 3+s mbe, rbe, pc 13 , pc 12 ? (sp+1) unconditional pc 11C0 ? (sp)(sp+3)(sp+2), sp ? sp+4 then skip unconditionally l m pd753012a, 753016a , , mbe, rbe ? (sp+4) 0, 0, pc 13 , pc 12 ? (sp+1) pc 11C0 ? (sp)(sp+3)(sp+2), sp ? sp+6 then skip unconditionally l m pd753017a , , mbe, rbe ? (sp+4) 0, pc 14 , pc 13 , pc 12 ? (sp+1) pc 11C0 ? (sp)(sp+3)(sp+2), sp ? sp+6 then skip unconditionally reti note !faddr 1 3 mbe, rbe, pc 13 , pc 12 ? (sp+1) pc 11C0 ? (sp)(sp+3)(sp+2) psw ? (sp+4)(sp+5), sp ? sp+6 l m pd753012a, 753016a 0, 0, pc 13 , pc 12 ? (sp+1) pc 11C0 ? (sp)(sp+3)(sp+2) psw ? (sp+4)(sp+5), sp ? sp+6 l m pd753017a 0, pc 14 , pc 13 , pc 12 ? (sp+1) pc 11C0 ? (sp)(sp+3)(sp+2) psw ? (sp+4)(sp+5), sp ? sp+6 note the above operations in the shaded boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. remark when the m pd753017a is set in the mk i mode, pc 14 is fixed to 0. 56 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine push rp 1 1 (spC1)(spC2) ? rp, sp ? spC2 stack control bs 2 2 (spC1) ? mbs, (spC2) ? rbs, sp ? spC2 pop rp 1 1 rp ? (sp+1)(sp), sp ? sp+2 bs 2 2 mbs ? (sp+1), rbs ? (sp), sp ? sp+2 interrupt ei 2 2 ime(ips.3) ? 1 control iexxx 2 2 iexxx ? 1 di 2 2 ime(ips.3) ? 0 iexxx 2 2 iexxx ? 0 input/output in note 1 a, portn 2 2 a ? portn (n = 0-7) xa, portn 2 2 xa ? portn+1, portn (n = 4, 6) out note 1 portn, a 2 2 portn ? a (n = 2-7) portn, xa 2 2 portn+1, portn ? xa (n = 4, 6) cpu control halt 2 2 set halt mode (pcc.2 ? 1) stop 2 2 set stop mode (pcc.3 ? 1) nop 1 1 no operation special sel rbn 2 2 rbs ? n (n = 0-3) mbn 2 2 mbs ? n (n = 0-3, 15) geti notes 2, 3 taddr 1 3 ? when tbr instruction *10 pc 13C0 ? (taddr) 5C0 +(taddr+1) ? when tcall instruction (spC4)(spC1)(spC2) ? pc 11C0 (spC3) ? mbe, rbe, pc 13 , pc 12 pc 13C0 ? (taddr) 5C0 +(taddr+1) sp ? spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed instruction 13 l m pd753017a ? when tbr instruction pc 13C0 ? (taddr) 5C0 +(taddr+1) pc 14 ? 0 4 ? when tcall instruction (spC6)(spC3)(spC4) ? pc 11C0 (spC5) ? 0, 0, pc 13, 12 (spC2) ? , , mbe, rbe pc 13C0 ? (taddr) 5C0 +(taddr+1) sp ? spC6, pc 14 ? 0 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed instruction notes 1. while the in instruction and out instruction are being executed, the mbe must be set to 0 or 1 and mbs must be set to 15. 2. the above operations in the shaded boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 3. the tbr and tcall instructions are the table definition assembler pseudo instructions of the geti instruction. remark when the m pd753017a is set in the mk i mode, pc 14 is fixed to 0. 57 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 12. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +7.0 v input voltage v i1 other than ports 4, 5 C0.3 to v dd + 0.3 v v i2 ports pull-up resistor provided C0.3 to v dd + 0.3 v 4, 5 n-ch open-drain C0.3 to +14 v output voltage v o C0.3 to v dd + 0.3 v high-level output current i oh per pin C10 ma total of all pins C30 ma low-level output current i ol per pin 30 ma total of all pins 220 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v 15 pf i/o capacitance c io 15 pf 58 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation frequency 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation after v dd has 4 ms stabilization time note 3 reached min. value of oscillation voltage range crystal oscillation frequency 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 30 external x1 input frequency 1.0 6.0 note 2 mhz clock (f x ) note 1 x1 input high-, 83.3 500 ns low-level width (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency shown above indicate characteristics of the oscillator only. for the instruction execution time, refer to ac characteristics . 2. if the oscillation frequency is 4.19 mhz < f x 6.0 mhz at 1.8 v v dd < 2.7 v, do not set the processor clock control register (pcc) to 0011. if pcc = 0011, one machine cycle time is less than 0.95 m s, falling short of the rated value of 0.95 m s. 3. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied or stop mode has been released. caution when using the main system clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground point of the capacitor of the oscillator at the same potential as v dd . do not ground to a power supply pattern through which a high current flows. do not extract signals from the oscillator. x1 x2 c1 c2 v dd x1 x2 c1 c2 v dd x1 x2 59 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 recommended oscillator constant ceramic resonator (t a = C20 to +80 c) manufacturer part number frequency recommended circuit oscillation voltage remarks (mhz) constant (pf) range (v) c1 c2 min. max. tdk corp. ccr1000k2 1.0 100 100 1.8 5.5 C ccr2.0mc33 2.0 C C on-chip capacitor ccr4.19mc3 4.19 fcr4.19mc5 ccr6.0mc3 6.0 murata mfg. csb1000j note 1.0 100 100 2.1 5.5 rd = 5.6 k w co., ltd. csa2.00mg040 2.0 100 100 1.9 C cst2.00mg040 C C on-chip capacitor csa4.19mg 4.19 30 30 1.8 C cst4.19mgw C C on-chip capacitor csa6.00mg 6.0 30 30 2.3 C cst6.00mgw C C on-chip capacitor kyocera corp. kbr-1000f/y 1.0 100 100 1.8 5.5 C kbr-2.0ms 2.0 68 68 kbr-4.0msa/msb 4.0 33 33 kbr-4.0mkc C C on-chip capacitor kbr-4.0mkd kbr-4.0mks pbrc4.00a 4.0 33 33 C pbrc4.00b C C on-chip capacitor kbr-4.19msa 4.19 33 33 C kbr-4.19msb 33 33 kbr-4.19mkc C C on-chip capacitor kbr-4.19mkd kbr-4.19mks pbrc4.19a 33 33 C pbrc4.19b C C on-chip capacitor kbr-6.0msa/msb 6.0 33 33 C kbr-6.0mkc C C on-chip capacitor kbr-6.0mkd kbr-6.0mks pbrc6.00a 33 33 C pbrc6.00b C C on-chip capacitor 60 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 note when using the csb1000j (1.0 mhz) by murata mfg. co., ltd. as a ceramic resonator, a limiting resistor (rd = 5.6 k w ) is necessary (refer to the figure below). the resistor is not necessary when using the other recommended resonators. x1 x2 c1 c2 rd csb1000j caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use. 61 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit circuit crystal oscillation frequency 32 32.768 35 khz resonator (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 ms stabilization time note 2 10 external xt1 input frequency 32 100 khz clock (f xt ) note 1 xt1 input high-, 5 15 m s low-level width (t xth , t xtl ) notes 1. the oscillation frequency shown above indicates characteristics of the oscillator only. for the instruction execution time, refer to ac characteristics . 2. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied. caution when using the subsystem clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground point of the capacitor of the oscillator at the same potential as v dd . do not ground to a power supply pattern through which a high current flows. do not extract signals from the oscillation circuit. the subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator. therefore, exercise utmost care in wiring the subsystem clock oscillator. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt1 xt2 c3 c4 v dd r xt1 xt2 62 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit low-level output i ol per pin 15 ma current total of all pins 150 ma high-level input v ih1 ports 2, 3 v dd = 2.7 to 5.5 v 0.7 v dd v dd v voltage v dd = 1.8 to 2.7 v 0.9 v dd v dd v v ih2 ports 0, 1, 6, 7, reset v dd = 2.7 to 5.5 v 0.8 v dd v dd v v dd = 1.8 to 2.7 v 0.9 v dd v dd v v ih3 ports 4, 5 pull-up resistor v dd = 2.7 to 5.5 v 0.7 v dd v dd v provided v dd = 1.8 to 2.7 v 0.9 v dd v dd v n-ch open-drain v dd = 2.7 to 5.5 v 0.7 v dd 13 v v dd = 1.8 to 2.7 v 0.9 v dd 13 v v ih4 x1, xt1 v dd C0.1 v dd v low-level input v il1 ports 2, 3, 4, 5 v dd = 2.7 to 5.5 v 0 0.3 v dd v voltage v dd = 1.8 to 2.7 v 0 0.1 v dd v v il2 ports 0, 1, 6, 7, reset v dd = 2.7 to 5.5 v 0 0.2 v dd v v dd = 1.8 to 2.7 v 0 0.1 v dd v v il3 x1, xt1 0 0.1 v high-level output v oh sck, so, ports 2, 3, 6, 7, bp0-bp7 i oh = C1 ma v dd C0.5 v voltage low-level output v ol1 sck, so, ports 2-7, i ol = 15 ma 0.2 2.0 v voltage bp0-bp7 v dd = 5.0 v 10% i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 n-ch open-drain 0.2 v dd v pull-up resistor 3 1 k w high-level input i lih1 v in = v dd pins other than x1, xt1, ports 4, 5 3 m a leakage current i lih2 x1, xt1 20 m a i lih3 v in = 13 v ports 4, 5 (n-ch open-drain) 20 m a low-level input i lil1 v in = 0 v pins other than x1, xt1, ports 4, 5 C3 m a leakage current i lil2 x1, xt1 C20 m a i lil3 ports 4, 5 (n-ch open-drain) C3 m a when input instruction is not executed ports 4, 5 (n-ch C30 m a open-drain) v dd = 5 v C10 C27 m a when input v dd = 3 v C3 C8 m a instruction is executed high-level output i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6, 7, 3 m a leakage current ports 4, 5 (pull-up resistor provided), bp0-bp7 i loh2 v out = 13 v ports 4, 5 (n-ch open-drain) 20 m a low-level output i lol v out = 0 v C3 m a leakage current internal pull-up r l1 v in = 0 v ports 0, 1, 2, 3, 6, 7 (except p00 pin) 50 100 200 k w resistor r l2 ports 4, 5 (mask option selected) 15 30 60 k w 63 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit lcd drive v lcd vac0 = 0 2.2 v dd v voltage note 1 vac0 = 1 1.8 v dd v vac current note 2 i vac vac0 = 1, v dd = 2.0 v 10% 1 4 m a lcd split r lcd1 50 100 200 k w resistor note 3 r lcd2 51020k w lcd output voltage v odc i o =v lcd0 = v lcd 0 0.2 v deviation note 4 1.0 m av lcd1 = v lcd 2/3 (common) v lcd2 = v lcd 1/3 lcd output voltage v ods i o = 1.8 v v lcd v dd 0 0.2 v deviation note 4 0.5 m a (segment) supply i dd1 v dd = 5.0 v 10% note 7 2.2 6.6 ma current notes 2, 5 v dd = 3.0 v 10% note 8 0.6 2.0 ma i dd2 halt v dd = 5.0 v 10% 0.72 2.1 ma mode v dd = 3.0 v 10% 0.27 0.8 ma i dd1 v dd = 5.0 v 10% note 7 1.7 5.1 ma v dd = 3.0 v 10% note 8 0.3 0.9 ma i dd2 halt v dd = 5.0 v 10% 0.7 2.0 ma mode v dd = 3.0 v 10% 0.23 0.7 ma i dd3 v dd = 3.0 v 10% 15 45 m a v dd = 2.0 v 10% 8 24 m a v dd = 3.0 v, t a = 25 c1530 m a v dd = 3.0 v 10% 12 36 m a v dd = 3.0 v, t a = 25 c1224 m a i dd4 halt v dd = 3.0 v 10% 8.5 25 m a mode v dd = 2.0 v 10% 412 m a v dd = 3.0 v, t a = 25 c 8.5 17 m a v dd = 3.0 v 10% 3.5 12 m a v dd = 3.0 v, t a = 25 c 3.5 7 m a i dd5 xt1 = v dd = 5.0 v 10% 0.05 10 m a 0 v note 12 v dd = 3.0 v 10% 0.02 5 m a stop mode t a = 25 c 0.02 3 m a notes 1. when 1.8 v v dd < 2.7 v, t a = C10 to +85 c. 2. clear vac0 to 0 in the low current consumption mode and stop mode. when vac0 is set to 1, the current increases by about 1 m a. 3. either r lcd1 or r lcd2 can be selected by mask option. 4. voltage deviation is the difference between the ideal values (v lcdn ; n = 0, 1, 2) of the segment and common outputs and the output voltage. 5. the current flowing through the internal pull-up resistor and the lcd divider resistor is not included. 6. including the case when the subsystem clock oscillates. 7. when the device operates in high-speed mode with the processor clock control register (pcc) set to 0011. 8. when the device operates in low-speed mode with pcc set to 0000. 9. when the device operates on the subsystem clock, with the system clock control register (scc) set to 1001 and oscillation of the main system clock stopped. 10. when the sub-oscillator control register (sos) is set to 0000. 11. when sos is set to 0010. 12. when sos is set to 00x1, and the feedback resistor of the sub-oscillator is not used (x: dont care). low current consumption mode note 11 6.00 mhz note 6 crystal oscillation c1 = c2 = 22 pf 4.19 mhz note 6 crystal oscillation c1 = c2 = 22 pf 32.768 khz note 9 crystal oscillation low voltage mode note 10 low voltage mode note 10 low current consumption mode note 11 64 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 ac characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cpu clock cycle time note 1 t cy operates with v dd = 2.7 to 5.5 v 0.67 64 m s (minimum instruction main system clock 0.95 64 m s execution time = 1 operates with 114 122 125 m s machine cycle) subsystem clock ti0, ti1, ti2 input frequency f ti v dd = 2.7 to 5.5 v 0 1 mhz 0 275 khz ti0, ti1, ti2 input high-, t tih , t til v dd = 2.7 to 5.5 v 0.48 m s low-level width 1.8 m s interrupt input high-, t inth , t intl int0 im02 = 0 note 2 m s low-level width im02 = 1 10 m s int1, 2, 4 10 m s kr0-kr7 10 m s reset low-level width t rsl 10 m s notes 1. the cycle time of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator, the system clock control register (scc), and processor clock control register (pcc). the figure on the right shows the supply voltage v dd vs. cycle time t cy characteristics when the device operates with the main system clock. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). 0 1 2 3 4 5 6 1 0.5 2 3 4 5 6 60 64 (with main system clock) t cy vs v dd operation guaranteed range cycle time t cy [ s] supply voltage v dd [v] 65 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 serial transfer operation 2-wire and 3-wire serial i/o modes (sck internal clock output): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-, low-level width t kl1 v dd = 2.7 to 5.5 v t kcy1 /2C50 ns t kh1 t kcy1 /2C150 ns si note 1 setup time t sik1 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns si note 1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns sck ? so note 1 t kso1 r l = 1 k w, v dd = 2.7 to 5.5 v 0 250 ns output delay time c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. 2-wire and 3-wire serial i/o modes (sck external clock input): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-, low-level width t kl2 v dd = 2.7 to 5.5 v 400 ns t kh2 1600 ns si note 1 setup time t sik2 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns si note 1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns sck ? so note 1 t kso2 r l = 1 k w, v dd = 2.7 to 5.5 v 0 300 ns output delay time c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. note 2 note 2 66 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 sbi mode (sck internal clock output (master)): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy3 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-, low-level width t kl3 v dd = 2.7 to 5.5 v t kcy3 /2C50 ns t kh3 t kcy3 /2C150 ns sb0, 1 setup time t sik3 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns sb0, 1 hold time (from sck - ) t ksi3 t kcy3 /2 ns sck ? sb0, 1 output t kso3 r l = 1 k w, v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf 0 1000 ns sck - ? sb0, 1 t ksb t kcy3 ns sb0, 1 ? sck t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns note r l and c l respectively indicate the load resistance and load capacitance of the sb0, 1 output line. sbi mode (sck external clock input (slave)): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy4 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-, low-level width t kl4 v dd = 2.7 to 5.5 v 400 ns t kh4 1600 ns sb0, 1 setup time t sik4 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns sb0, 1 hold time (from sck - ) t ksi4 t kcy4 /2 ns sck ? sb0, 1 output t kso4 r l = 1 k w, v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf 0 1000 ns sck - ? sb0, 1 t ksb t kcy4 ns sb0, 1 ? sck t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l respectively indicate the load resistance and load capacitance of the sb0, 1 output line. note note 67 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 ac timing test points (except x1 and xt1 inputs) clock timing ti0, ti1, ti2 timing 1/f x t xl t xh v dd ?0.1 v 0.1 v x1 input 1/f xt t xtl t xth v dd ?0.1 v 0.1 v xt1 input 1/f ti t til t tih ti0, ti1, ti2 v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) 68 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode t kcy1,2 t kl1,2 t kh1,2 sck output data so input data si t sik1,2 t ksi1,2 t kso1,2 t kcy1,2 t kl1,2 t kh1,2 sck sb0, 1 t sik1,2 t ksi1,2 t kso1,2 69 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 serial transfer timing bus release signal transfer command signal transfer interrupt input timing reset input timing int0, 1, 2, 4 kr0-7 t intl t inth sck sb0, 1 t kcy3, 4 t sik3, 4 t kso3, 4 t ksi3, 4 t sbk t sbh t sbl t ksb t kh3, 4 t kl3, 4 sck sb0, 1 t kcy3, 4 t sik3, 4 t kso3, 4 t kl3, 4 t kh3, 4 t ksi3, 4 t sbk t ksb reset t rsl 70 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 data retention characteristics of data memory in stop mode and at low supply voltage (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply v dddr 1.8 5.5 v voltage release signal setup time t srel 0 m s oscillation stabilization t wait released by reset note 2 ms wait time note 1 released by interrupt request note 3 ms notes 1. the oscillation stabilization wait time is the time during which the cpu stops operating to prevent unstable operation when oscillation is started. 2. either 2 17 /f x or 2 15 /f x can be selected by mask option. 3. set by the basic interval timer mode register (btm). (refer to the table below.) btm3 btm2 btm1 btm0 wait time f x = 4.19 mhz f x = 6.0 mhz C0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) C0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) C1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) C1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) data retention timing (when stop mode released by reset) data retention timing (standby release signal: when stop mode released by interrupt signal) stop mode data retention mode operation mode halt mode t srel v dddr t wait stop instruction execution v dd standby release signal (interrupt request) stop mode data retention mode internal reset operation operation mode stop instruction execution halt mode v dd reset v dddr t wait t srel 71 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 13. characteristics curves (reference values) i dd vs v dd (f x = 4.19 mhz, f xt = 32.768 khz) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0 1 1.8 23 45 5.5 6 7 pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 main system clock halt mode + 32 khz oscillation supply current i dd (ma) subsystem clock operation mode (sos.1 = 0) subsystem clock halt mode (sos.1 = 1) main system clock stop mode + 32 khz oscillation (sos.1 = 1) crystal resonator 4.19 mhz crystal resonator 32.768 mhz 330 k w 22 pf 22 pf v ss v ss (t a = 25 c) supply voltage v dd (v) 22 pf 22 pf x1 x2 xt1 xt2 72 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 i oh vs v dd ? oh (ports 2, 3, 6, 7) (t a = 25 c) i ol vs v ol (ports 2, 3, 6, 7) (t a = 25 c) 15 10 5 0 i oh [ma] 40 30 20 10 0 i ol [ma] 0 0.5 1.0 1.5 2.0 2.5 3.0 v dd ? oh [v] 0 0.5 1.0 1.5 2.0 v ol [v] v dd = 5 v v dd = 4 v v dd = 5.5 v v dd = 3 v v dd = 2.2 v v dd = 1.8 v v dd = 5 v v dd = 4 v v dd = 5.5 v v dd = 3 v v dd = 2.2 v v dd = 1.8 v 73 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 14. package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.4 14.0 0.2 0.13 0.825 i 17.2 0.4 j c 14.0 0.2 h 0.30 0.10 0.65 (t.p.) k 1.6 0.2 l 0.8 0.2 f 0.825 s80gc-65-3b9-6 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. m 0.15 + 0.10 - 0.05 60 61 40 80 1 21 20 41 s s n j detail of lead end c d a b r k m l p i s q g f m h 74 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 - 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 - 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h 75 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 20 1 s 80 pin plastic tqfp (fine pitch) (12x12) item millimeters i j 0.50 (t.p.) 0.10 a 14.00 0.20 b 12.00 0.20 c 12.00 0.20 d 14.00 0.20 f g 1.25 1.25 h 0.22 p80gk-50-be9-6 s 1.27 max. k 1.00 0.20 l 0.50 0.20 m 0.145 n 0.10 p 1.05 0.07 q 0.10 0.05 r5 5 +0.05 ?.04 +0.055 ?.045 j ns l k m detail of lead end 61 60 41 40 21 80 a b c d s qr g f p hi m note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 76 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f 1.25 14.0 0.2 b 12.0 0.2 m n 0.08 0.145 0.05 p q 0.1 0.05 1.0 j 0.5 (t.p.) k l 0.5 1.0 0.2 i 0.08 s 1.1 0.1 r 3 + 4 - 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u 0.6 0.15 77 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 15. recommended soldering conditions solder the m pd753017a under the following recommended conditions. for the details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for the soldering methods and conditions other than those recommended, consult nec. table 15-1. soldering conditions of surface mount type (1/2) (1) m pd753012agc-xxx-3b9: 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd753016agc-xxx-3b9: 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd753017agc-xxx-3b9: 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below ir35-00-3 (210 c or higher), number of reflow processes: 3 max. vps package peak temperature: 215 c, reflow time: 40 seconds or below vp15-00-3 (200 c or higher), number of reflow processes: 3 max. wave soldering solder temperature: 260 c or below, time: 10 seconds or below, ws60-00-1 number of flow processes: 1 preheating temperature: 120 c or below (package surface temperature) partial heating pin temperature: 300 c or below, time: 3 seconds or below C (per side of device) (2) m pd753012agc-xxx-8bt: 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd753016agc-xxx-8bt: 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd753017agc-xxx-8bt: 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below ir35-00-2 (210 c or higher), number of reflow processes: 2 max. vps package peak temperature: 215 c, reflow time: 40 seconds or below vp15-00-2 (200 c or higher), number of reflow processes: 2 max. wave soldering solder temperature: 260 c or below, time: 10 seconds or below, ws60-00-1 number of flow processes: 1 preheating temperature: 120 c or below (package surface temperature) partial heating pin temperature: 300 c or below, time: 3 seconds or below C (per side of device) caution do not use two or more soldering methods in combination (except the partial heating method). 78 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 table 15-1. soldering conditions of surface mount type (2/2) (3) m pd753012agk-xxx-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd753016agk-xxx-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd753017agk-xxx-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below ir35-107-3 (210 c or higher), number of reflow processes: 3 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours.) vps package peak temperature: 215 c, reflow time: 40 seconds or below vp15-107-3 (200 c or higher), number of reflow processes: 3 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours.) partial heating pin temperature: 300 c or below, time: 3 seconds or below C (per side of device) note the number of days for storage after the dry pack has been opened. the storage conditions are 25 c, 65% rh max. (4) m pd753012agk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.00 mm) m pd753016agk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.00 mm) m pd753017agk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.00 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below ir35-107-2 (210 c or higher), number of reflow processes: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours.) vps package peak temperature: 215 c, reflow time: 40 seconds or below vp15-107-2 (200 c or higher), number of reflow processes: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours.) partial heating pin temperature: 300 c or below, time: 3 seconds or below C (per side of device) note the number of days for storage after the dry pack has been opened. the storage conditions are 25 c, 65% rh max. caution do not use two or more soldering methods in combination (except the partial heating method). 79 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 appendix a. m pd75316b, 753017a and 75p3018a function list parameter m pd75316b m pd753017a m pd75p3018a program memory mask rom mask rom one-time prom 0000h-3f7fh 0000h-5fffh 0000h-7fffh (16256 8 bits) (24576 8 bits) (32768 8 bits) data memory 000h-3ffh (1024 4 bits) cpu 75x standard 75xl cpu instruction when main system 0.95, 1.91, 15.3 m s ? 0.95, 1.91, 3.81, 15.3 m s (at 4.19 mhz operation) execution clock is selected (at 4.19 mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (at 6.0 mhz operation) time when subsystem 122 m s (32.768 khz operation) clock is selected pin 44 p12/int2 p12/int2/ti1/ti2 connection 47 p21 p21/pto1 48 p22/pcl p22/pcl/pto2 50-53 p30-p33 p30/md0-p33/md3 57 ic v pp stack sbs register none sbs.3 = 1: mk i mode selection sbs.3 = 0: mk ii mode selection stack area 000h-0ffh n00h-nffh (n = 0-3) subroutine call 2-byte stack mk i mode: 2-byte stack instruction stack mk ii mode: 3-byte stack operation instruction bra !addr1 unavailable mk i mode: unavailable calla !addr1 mk ii mode: available movt xa, @bcde available movt xa, @bcxa br bcde br bcxa call !addr 3 machine cycles mk i mode: 3 machine cycles, mk ii mode: 4 machine cycles callf !faddr 2 machine cycles mk i mode: 2 machine cycles, mk ii mode: 3 machine cycles timer 3 channels 5 channels ? basic interval timer: ? basic interval timer/watchdog timer: 1 channel 1 channel ? 8-bit timer/event counter: 3 channels ? 8-bit timer/event counter: (can be used as 16-bit timer/event counter, 1 channel carrier generator, timer with gate) ? watch timer: 1 channel ? watch timer: 1 channel 80 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 parameter m pd75316b m pd753017a m pd75p3018a clock output (pcl) f , 524, 262, 65.5 khz ? f , 524, 262, 65.5 khz (main system clock: (main system clock: at 4.19 mhz operation) at 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: at 6.0 mhz operation) buz output 2 khz ? 2, 4, 32 khz (main system clock: (main system clock: at 4.19 mhz operation or at 4.19 mhz operation) subsystem clock: at 32.768 khz operation) ? 2.93, 5.86, 46.9 khz (main system clock: at 6.0 mhz operation) serial interface 3 modes are available ? 3-wire serial i/o mode ... msb/lsb can be selected for transfer first bit ? 2-wire serial i/o mode ? sbi mode sos feedback resistor cut flag none provided register (sos.0) sub-oscillator current cut none provided flag (sos.1) register bank selection register (rbs) none yes standby release by int0 unavailable available interrupt priority selection register (ips) none yes vectored interrupt external: 3, internal: 3 external: 3, internal: 5 supply voltage v dd = 2.0 to 6.0 v v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85?c package ? 80-pin plastic tqfp (fine pitch) (12 12 mm) ? 80-pin plastic qfp (14 14 mm) 81 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 appendix b. development tools the following development tools are provided for system development using the m pd753017a. the 75xl series uses a common relocatable assembler, in combination with a device file matching each machine. language processor ra75x relocatable assembler host machine part number os supply media (product name) pc-9800 series ms-dos tm 3.5-inch 2hd m s5a13ra75x ver. 3.30 to ver. 6.2 note ibm pc/at tm and refer to 3.5-inch 2hc m s7b13ra75x compatible machines os for ibm pc device file host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13df753017 ver. 3.30 to ver. 6.2 note ibm pc/at and refer to 3.5-inch 2hc m s7b13df753017 compatible machines os for ibm pc note ver. 5.00 or later is provided with a task swap function, but it does not work with this software. remark the operation of the assembler and device file is guaranteed only on the above host machines and oss. 82 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 prom write tools hardware pg-1500 pg-1500 is a prom programmer which enables you to program single-chip microcontroller containing prom by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to pg-1500. it also enables you to program typical prom devices of 256k bits to 4m bits. pa-75p316bgc prom programmer adapter common to m pd75p3018gc-3b9. connect the programmer adapter to pg-1500 for use. pa-75p316bgk prom programmer adapter common to m pd75p3018gk-be9. connect the programmer adapter to pg-1500 for use. pa-75p3018agc-8bt prom programmer adapter common to m pd75p3018agc-8bt. connect the programmer adapter to pg-1500 for use. pa-75p3018agk-9eu prom programmer adapter common to m pd75p3018agk-9eu. connect the programmer adapter to pg-1500 for use. software pg-1500 controller pg-1500 and a host machine are connected by serial and parallel interfaces and pg-1500 is controlled on the host machine. host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 ver. 3.30 to ver. 6.2 note ibm pc/at and refer to 3.5-inch 2hd m s7b13pg1500 compatible machines os for ibm pc note ver.5.00 or later is provided with a task swap function, but it does not work with this software. remark the operation of the pg-1500 controller is guaranteed only on the above host machines and oss. 83 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 debugging tool the in-circuit emulators (ie-75000-r and ie-75001-r) are available as the program debugging tool for the m pd753017a. the system configurations are described as follows. hardware ie-75000-r note 1 in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd753017 subseries, the emulation board ie-75300-r-em and emulation probe that are sold separately must be used with the ie-75000-r. by connecting with the host machine and the prom programmer, efficient debugging can be made. it contains the emulation board ie-75000-r-em which is connected. ie-75001-r in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd753017 subseries, the emulation board ie-75300-r-em and emulation probe which are sold separately must be used with the ie-75001-r. it can debug the system efficiently by connecting the host machine and prom programmer. ie-75300-r-em emulation board for evaluating the application systems that use the m pd753017 subseries. it must be used with the ie-75000-r or ie-75001-r. ep-753017gc-r emulation probe for the m pd753017agc. it must be connected to the ie-75000-r (or ie-75001-r) and ie-75300-r-em. it is supplied with the 80-pin conversion socket ev-9200gc-80 which facilitates ev-9200gc-80 connection to a target system. ep-753017gk-r emulation probe for the m pd753017agk. it must be connected to the ie-75000-r (or ie-75001-r) and ie-75300-r-em. it is supplied with the 80-pin conversion adapter tgk-080sdw which facilitates tgk-080sdw note 2 connection to a target system. software ie control program connects the ie-75000-r or ie-75001-r to a host machine via rs-232-c and centronix i/f and controls the ie-75000-r or ie-75001-r on a host machine. host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13ie75x ver. 3.30 to 5-inch 2hd m s5a10ie75x ver. 6.2 note 3 ibm pc/at and refer to 3.5-inch 2hc m s7b13ie75x compatible machines os for ibm pc 5-inch 2hc m s7b10ie75x notes 1. maintenance parts 2. this is a product of tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics 2nd department (tel +81-6-6244-6672) 3. ver.5.00 or later is provided with a task swap function, but it dose not work with this software. remarks 1. the operation of the ie control program is guaranteed only on the above host machines and oss. 2. the m pd753012, 753016, 753017, 75p3018, 753012a, 753016a, 753017a, and 75p3018a are commonly referred to as the m pd753017 subseries. 84 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 os for ibm pc the following ibm pc oss are supported. os version pc dos tm ver. 5.02 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note only english version is supported. caution ver. 5.0 or later is provided with a task swap function, but it does not work with this software. 85 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 appendix c. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document name document no. japanese english m pd753012a, 753016a, 753017a data sheet u11662j u11662e (this document) m pd75p3018a data sheet u11917j u11917e m pd753017 users manual u11282j u11282e m pd753017 instruction table iem-5598 75xl series selection guide u10453j u10453e development tool related documents document name document no. japanese english hardware ie-75000-r/ie-75001-r users manual eeu-846 eeu-1416 ie-75300-r-em users manual u11354j eeu-1493 ep-753017gc/gk-r users manual eeu-967 eeu-1495 pg-1500 users manual u11940j u11940e software ra75x assembler package operation u12622j u12622e users manual language u12385j u12385e pg-1500 controller users manual pc-9800 series eeu-704 eeu-1291 (ms-dos) base ibm pc series eeu-5008 u10540e (pc dos) base other related documents document name document no. japanese english semiconductor selection guide products & package (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic c11892j c11892e discharge (esd) guide to microcontroller-related products by third parties u11416j C caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. 86 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 87 m pd753012a, 753016a, 753017a data sheet u11662ej2v0ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1 m pd753012a, 753016a, 753017a ms-dos is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of april, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). |
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